R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 540

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing
• Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary
Rev. 2.00 Sep. 07, 2007 Page 512 of 1164
REJ09B0321-0200
Figure 12.57 Example of Procedure for Setting Output Waveform Control at Synchronous
in Complementary PWM Mode
An example of the procedure for setting output waveform control at synchronous counter
clearing in complementary PWM mode is shown in figure 12.57.
PWM Mode
Figures 12.58 to 12.61 show examples of output waveform control in which the MTU2
operates in complementary PWM mode and synchronous counter clearing is generated while
the WRE bit in TWCR is set to 1. In the examples shown in figures 12.58 to 12.61,
synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 12.56,
respectively.
synchronous counter clearing
synchronous counter clearing
complementary PWM mode
Output waveform control at
Output waveform control at
Start count operation
Stop count operation
Set TWCR and
Counter Clearing in Complementary PWM Mode
[1]
[2]
[3]
[1] Clear bits CST3 and CST4 in the timer
[2] Read bit WRE in TWCR and then write 1
[3] Set bits CST3 and CST4 in TSTR to 1 to
start register (TSTR) to 0, and halt timer
counter (TCNT) operation. Perform
TWCR setting while TCNT_3 and
TCNT_4 are stopped.
to it to suppress initial value output at
counter clearing.
start count operation.