R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 263

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

"Transition to or recovery from in progress" refers to the interval from the point at which the bits
listed in table 9.5 are written to until the corresponding commands are issued.
Table 9.5
Note: Execution of a self-refresh, a transition to or recovery from power-down or deep-power-
Bit
2
1
0
Function
Self-refresh
Initialization sequence
Power-down
Deep-power-down
Mode register setting
down mode, an initialization sequence, or mode register setting may only be performed
when all status bits are cleared to 0. Do not rewrite the registers (bits) listed below when
any of the status bits (DSRFST, DINIST, DPWDST, DDPDST, DMRSST) is set to 1.
Bit Name
DPWDST
DDPDST
DMRSST
List of Status Registers and Bits Requiring Checking
0
0
0
Initial
Value
Register
SDRFCNT0
SDIR1
SDmMOD
SDPWDCNT
SDDPDCNT
R/W
R
R
R
Description
Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from power-down mode is in progress for a
channel from SDRAM0 to SDRAM3.
0: Initialization sequence not in progress
1: Initialization sequence in progress
Deep-Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from deep-power-down mode is in progress
for channel SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
Mode Register Setting Status
When set to 1, this bit indicates that mode register
setting is in progress for channel SDRAM0 or
SDRAM1.
0: Mode register setting not in progress
1: Mode register setting in progress
Rev. 2.00 Sep. 07, 2007 Page 235 of 1164
Bits
DSFENCm, DSFEN
DINIRQCm, DINIRQ
DPWDCm, DPWD
DDPDCm, DDPD
DMR
Section 9 Bus State Controller (BSC)
REJ09B0321-0200