R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 71

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
Instruction
Indicated by mnemonic.
Explanation of Symbols
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement*
Destination register
2. Depending on the operand size, displacement is scaled by ×1, ×2, or ×4. For details,
practice, the number of instruction execution states will be increased in cases such as
the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is the same
refer to the SH-2A, SH2A-FPU Software Manual.
as the register used by the next instruction.
2
Instruction Code
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Memory operand
Rev. 2.00 Sep. 07, 2007 Page 43 of 1164
Execution
States
Value when no
wait states are
inserted. *
1
REJ09B0321-0200
T Bit
Value of T bit after
instruction is
executed.
Explanation of
Symbols
—: No change
Section 2 CPU