R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 33

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
Direct memory access
controller (DMAC)
Clock pulse
generator (CPG)
Watchdog timer
(WDT)
Features
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Eight channels; external request available for four of them
Can be activated by software, on-chip modules, or external devices
 Software; 1, internal source; 32, external source; 4
Up to 64 Mbytes can be transferred
Maximum transfer data size
 8, 16, or 32 bits for single-data transfer
 1, 2, 4, 8, 16, 32, 64, or 128 sets of data for single operand transfer
Transfer method
 Cycle-stealing transfer (dual address transfer)
 Pipeline transfer (dual address transfer)
Addressing method
Increment, decrement, or fixed
Three clock cycles per one set of data (best)
Transfer modes
Single operand transfer, continuous operand transfer, and non-stop
transfer
An interrupt is requested when the byte count reaches 0
Reloading function
Source address, destination address, and byte count
DMAC suspend, resume, and stop function
DMAC forcible terminate function
Clock mode: Input clock can be selected from external input (EXTAL
or CKIO) or crystal resonator
Input clock can be multiplied by 16 (max.) by the internal PLL circuit
Three types of clocks generated
CPU clock: Maximum 120 MHz
Bus clock: Maximum 60 MHz
Peripheral clock: Maximum 40 MHz
On-chip one-channel watchdog timer
A counter overflow can reset this LSI
(a transfer continues until the byte count reaches 0)
Three clock cycles per one set of data (best)
Bus released between read and write cycles
One clock cycle per one set of data (best)
Rev. 2.00 Sep. 07, 2007 Page 5 of 1164
Section 1 Overview
REJ09B0321-0200