R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 387

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.8
11.8.1
Channel priority is allocated in descending order from channel 0; that is priority follows the below
relation, where P indicates priority.
P
11.8.2
The DMAC determines the priority every time single operand transfer is performed.
When a DMA request with a higher priority is generated during transfer for one channel, the
transfer for the higher-priority channel only starts after the end of the current operand transfer.
Figure 11.10 shows overall operation when multiple DMA requests are generated. The thick lines
in the figure indicate the periods over which the DMA request signals are at the low level. Here
channels 0, 2 and 3 are set to a level sense and channel 1 is set to an edge sense.
1. Since the channel 2 request is masked, it is regarded as non-existent. Thus, transfer on channel
2. Since channel 0 has the highest priority, transfer on this channel starts up.
3. Since channel 2 has the higher priority of the requests at this point, transfer on this channel
4. Transfer on channel 3 is restarted as there are no other requests at this point.
5. When the DMA requests are simultaneously generated for channels 0, 1, and 3, transfer on
6. After the transfer on channel 0 is complete, transfer on channel 1 starts up because it has the
7. A further DMA request (the selected edge) is received on channel 1 while DMA transfer is in
8. On completion of the transfer on channel 1, transfer on channel 3 starts up since there are no
9. No transfer starts up immediately after the end of the unit transfer operation on channel, since
channel 0
3 starts up.
restarts.
channel 0 starts up because it has the highest priority.
second highest priority.
progress. Transfer on channel 1 is thus restarted after completion of the current round of
transfer on channel 1. No masking period applies in the case of edge sensing.
other requests.
channel 3 requests are masked and there are no other requests. Transfer on channel 3 only
restarts after the end of the masking period.
> P
Determining DMA Channel Priority
Channel Priority Order
Operation during Multiple DMA Requests
channel 1
> P
channel 3
… P
channel 6
> P
channel 7
. This order is fixed.
Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Sep. 07, 2007 Page 359 of 1164
REJ09B0321-0200