R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 255

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.10
SDIR1 controls activation of the SDRAM initialization sequence.
Bit
31 to 17 
16
15 to 1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAM Initialization Register 1 (SDIR1)
Bit Name

DINIRQ
DINIST
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
29
13
—
—
0
0
Initial
Value
All 0
All 0
R
R
0
0
28
—
12
—
R
R
0
0
27
—
11
—
R
R
0
0
R/W
R
R/W
R
R/W
26
—
10
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Initialization Status
When set to 1, this bit indicates that an SDRAM
initialization sequence is in progress for channel
SDRAM0 or SDRAM1.
0: Initialization sequence not progress
1: Initialization sequence in progress
Reserved
These bits are always read as 0. The write value
should always be 0.
Common Initialization Sequence Start
Setting this bit to 1 causes the SDRAM initialization
sequence to start and automatically sets the
initialization status bit (DINIST) to 1. The initialization
status bit (DINIST) is cleared automatically after the
initialization sequence ends. The value written to the
DINIRQ bit is not retained.
0: Invalid
1: Initialization sequence start
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 227 of 1164
22
—
—
R
R
0
6
0
Section 9 Bus State Controller (BSC)
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
REJ09B0321-0200
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
R/W
R/W
DIN
DIN
IRQ
IST
16
0
0
0