R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 296

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
(d) Timing Register Set Values and Access Timing
The correspondence between the SDRAMm timing register (SDmTR) set values and the read and
write access timing is described below.
• Multiple Read Timing Setting Examples
Table 9.12 SDITR Set Value Correspondence Table (Multiple Read Timing)
Rev. 2.00 Sep. 07, 2007 Page 268 of 1164
REJ09B0321-0200
Figure
Figure 9.30
Figure 9.31
Figure 9.32
Figures 9.30 to 9.32 show the correspondence between the timing of multiple read operations
involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table
9.12 shows the SDRAMm timing register (SDmTR) set values for each figure.
CKIO
SDRAM command
Data bus
DRAS
010
000
000
Figure 9.30 Multiple Read Timing Example 1
ACT: Row and bank activation command
RD:
PRA: Precharge-all command
(ACT-RD)
DRCD
ACT
Read command
(ACT-PRA)
DRAS
RD
DRCD
00
01
01
(RD-d)
DCL
RD
Multiple read
RD
d0
DPCG
001
001
001
RD
d1
PRA
d2
(PRA-next)
DPCG
DSL
d3
DCL
010
010
011