R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 469
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
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Note:
Table 12.32 Setting of Bits BF1 and BF0
Table 12.33 TIOC4D Output Level Select Function
Note: The reverse phase waveform initial output value changes to the active level after elapse of
Bit
0
Bit 7
BF1
0
0
1
1
Bit 5
OLS3N
0
1
the dead time after count start.
*
Bit Name
OLS1P
Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid.
Initial Output
High level
Low level
Bit 6
BF0
0
1
0
1
Initial
value
0
Complementary PWM Mode
Does not transfer data from the
buffer register (TOLBR) to TOCR2.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest of the TCNT_4 count.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
trough of the TCNT_4 count.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest and trough of the TCNT_4
count.
Active Level
Low level
High level
R/W
R/W
Description
Output Level Select 1P*
This bit selects the output level on TIOC3B in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.38.
Up Count
High level
Low level
Function
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Description
Rev. 2.00 Sep. 07, 2007 Page 441 of 1164
Compare Match Output
Reset-Synchronized PWM Mode
Does not transfer data from the
buffer register (TOLBR) to TOCR2.
Transfers data from the buffer
register (TOLBR) to TOCR2 when
TCNT_3/TCNT_4 is cleared
Setting prohibited
Setting prohibited
Down Count
Low level
High level
REJ09B0321-0200
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