R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 896

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET)
19.9
19.9.1
The standby control register 2 (STBCR2) controls the supply of clocks to RCAN-ET. As an initial
value, the clock to RCAN-ET is halted. Registers should be accessed after the module stop mode
is released.
19.9.2
Two types of resets are supported for RCAN-ET.
• Hardware reset
• Software reset
As the IRR0 bit in the interrupt request register (IRR) is initialized and set to 1 at a reset, it should
be cleared to 0 in the configuration mode shown in the reset sequence diagram.
The area except for the message control field 1 (CONTROL1) of Mailbox is consisted of RAM,
and not initialized at a reset. After a power-on reset, all the Mailboxes should be initialized in the
configuration mode shown in the reset sequence diagram.
19.9.3
The supply of main clocks in the modules is stopped in CAN sleep mode. Therefore, registers
other than MCR, GSR, IRR, and IMR should not be accessed in CAN sleep mode.
19.9.4
When the CAN bus receive frame is being stored in the Mailbox with the CAN communication
functions of RCAN-ET, accessing the Mailbox area generates 0 to 5 peripheral bus cycles as a
wait.
Rev. 2.00 Sep. 07, 2007 Page 868 of 1164
REJ09B0321-0200
RCAN-ET is initialized by a power-on reset, deep standby mode, or software standby mode.
The MCR0 bit in the master control register (MCR) initializes registers other than MCR and
CAN communication functions.
Usage Notes
Module Standby Mode
Reset
CAN Sleep Mode
Register Access