R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 180

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
Rev. 2.00 Sep. 07, 2007 Page 152 of 1164
REJ09B0321-0200
IRQ
RESBANK instruction
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
Figure 6.7 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted
Instruction Execution (Register Banking without Register Bank Overflow)
Vector address read
Saving of SR (stack)
Saving of PC (stack)
2 Icyc + 3 Bcyc + 1 Pcyc
(Register Banking without Register Bank Overflow)
F
2 Icyc + 3 Bcyc + 1 Pcyc
D
E
E
Interrupt acceptance
E
F
9 Icyc
E
D
E
3 Icyc
3 Icyc + m1 + m2
E
E
Interrupt acceptance
E
E
E
m1
M
D
E
3 Icyc + m1 + m2
m2
M
E
m3
E
M
F
m1 m2 m3
M
E
D
M
E
M
F
E
D