R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 247

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.6
CS2WCNTn specifies the number of wait states and the number of delay cycles.
Bit
31
30 to 28 CSON
27
26 to 24 WDON
23
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6)
Bit Name

[2:0]

[2:0]

31
15
—
—
R
R
0
0
R/W
30
14
—
R
0
0
CSON[2:0]
R/W
29
13
Initial
Value
0
000
0
000
0
—
R
0
0
R/W
28
12
—
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R/W
R
R/W
R
R/W
R/W
26
10
0
0
WDOFF[2:0]
WDON[2:0]
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
CS Assert Wait Select
These bits specify the number of wait states inserted
before the external chip select signal (CSn) is asserted.
000: 0 wait state
111: 7 wait states
Reserved
This bit is always read as 0. The write value should
always be 0.
Write Data Output Wait Select
These bits specify the number of wait states inserted
before data is output to the external data bus.
000: 0 wait state
111: 7 wait states
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
R/W
25
0
9
0
:
:
R/W
R/W
24
0
8
0
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 219 of 1164
R/W
R/W
22
0
6
0
CSWOFF[2:0]
WRON[2:0]
Section 9 Bus State Controller (BSC)
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
19
—
—
R
R
0
3
0
REJ09B0321-0200
R/W
R/W
18
0
2
1
CSROFF[2:0]
RDON[2:0]
R/W
R/W
17
0
1
1
R/W
R/W
16
0
0
1