R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 318

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
Table 10.2 Bus Space and Slave Bus
Notes: 1. This means bus spaces in the slave bus space other than those for the external bus
Rev. 2.00 Sep. 07, 2007 Page 290 of 1164
REJ09B0321-0200
Bit
9, 8
7 to 0
Address
H'0000 0000 to H'4FFF FFFF
H'5000 0000 to H'E800 FFFF
H'E801 0000 to H'EFFF FFFF
H'F000 0000 to H'F1FF FFFF
H'F200 0000 to H'F5FF FFFF
H'F600 0000 to H'FF3F FFFF
H'FF40 0000 to H'FF5F FFFF
H'FF60 0000 to H'FFF7 FFFF
H'FFF8 0000 to H'FFF8 7FFF
H'FFF8 8000 to H'FFFB FFFF
H'FFFC 0000 to H'FFFF FFFF
2. An illegal address access error does not occur.
Bit Name
PMST[1:0]

and peripheral buses (1) and (2).
Initial
Value
00
All 0
Bus Space
External bus space
Reserved
Reserved
Address array space in cache
Reserved
Reserved
On-chip peripheral module (1)
Reserved
On-chip RAM
Reserved
On-chip peripheral module (2)
R/W
R
R
Description
Bus Master
These bits indicate the bus master that accessed
peripheral bus (1) when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Slave Bus
External bus
(Others*
(Others*
*
*
(Others*
Peripheral bus (1)
(Others*
*
*
Peripheral bus (2)
2
2
2
2
1
1
1
1
)
)
)
)