R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 451

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.3.9
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests
and specifies whether to link A/D converter start requests with interrupt skipping operation. The
MTU2 has one TADCR in channel 4.
Bit
2
1
0
Initial value:
Note:
R/W:
*
Bit:
Bit Name
I2AE
I1BE
I1AE
Timer A/D Converter Start Request Control Register (TADCR)
Do not set to 1 when complementary PWM mode is not selected.
R/W
15
0
BF[1:0]
R/W
14
0
13
—
R
0
Initial
Value
0
0
0
12
—
R
0
11
—
R/W
R/W
R/W
R/W
R
0
10
—
R
0
Description
Input Capture Enable
Specifies whether to include the TIOC2A pin in the
TGRA_1 input capture conditions.
0: Does not include the TIOC2A pin in the TGRA_1
1: Includes the TIOC2A pin in the TGRA_1 input
Input Capture Enable
Specifies whether to include the TIOC1B pin in the
TGRB_2 input capture conditions.
0: Does not include the TIOC1B pin in the TGRB_2
1: Includes the TIOC1B pin in the TGRB_2 input
Input Capture Enable
Specifies whether to include the TIOC1A pin in the
TGRA_2 input capture conditions.
0: Does not include the TIOC1A pin in the TGRA_2
1: Includes the TIOC1A pin in the TGRA_2 input
—
R
9
0
capture conditions
capture conditions
capture conditions
input capture conditions
input capture conditions
input capture conditions
—
R
8
0
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
R/W
7
0
Rev. 2.00 Sep. 07, 2007 Page 423 of 1164
R/W
0*
6
R/W
5
0
R/W
0*
4
R/W
0*
3
R/W
REJ09B0321-0200
0*
2
R/W
0*
1
R/W
0*
0