R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 50

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
(2)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3)
VBR is referenced as the branch destination base address in the event of an exception or an
interrupt.
(4)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
2.1.3
The system registers consist of four 32-bit registers: the high and low multiply and accumulate
registers (MACH and MACL), the procedure register (PR), and the program counter (PC). MACH
and MACL store the results of multiply or multiply and accumulate operations. PR stores the
return address from a subroutine procedure. PC indicates the program address being executed and
controls the flow of the processing.
(1)
MACH and MACL are used as the addition value in a MAC instruction, and store the result of a
MAC or MUL instruction.
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Global Base Register (GBR)
Vector Base Register (VBR)
Jump Table Base Register (TBR)
Multiply and Accumulate Register High (MACH) and Multiply and Accumulate
Register Low (MACL)
System Registers
MACH
MACL
PR
PC
Figure 2.3 System Registers
0
0
0
Multiply and accumulate register high (MACH) and multiply
and accumulate register low (MACL):
Store the results of multiply or multiply and accumulate operations.
Procedure register (PR):
Stores the return address from a subroutine procedure.
Program counter (PC):
Indicates the four bytes ahead of the current instruction.