R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 380

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.5.3
The form in which the DMA end signal (DTENDm) is output differs with the setting of the DMA
end signal output control bit (DTCM) in the DMA mode register (DMMODn) for the
corresponding channel.
• When DTCM is set to "00", output of the DTEND signal is not valid so the signal remains
• When DTCM is set to "01", the DTEND signal becomes active (low) one cycle after the start
• When DTCM is set to "10", the DTEND signal becomes active for one cycle after the write
• When DTCM is set to "11", the DTEND signal becomes active for one clock cycle at the same
Output of the DTEND signal is not valid in the case of DMA requests from external peripheral
circuits, so the signal remains fixed to "H" regardless of the setting of this bit.
Charts of the timing of DMA end signal output are given in figure 11.5.
Note: The BSC is provided with a write buffer. Writing data to this buffer while writing to the
Rev. 2.00 Sep. 07, 2007 Page 352 of 1164
REJ09B0321-0200
fixed at the "H" level when and after the DMA transfer ends.
of the read cycle immediately before the end of DMA transfer (the read cycle for the last data
transfer).
cycle immediately before the end of DMA transfer (the write cycle for the last data transfer).
time as the DMA transfer end interrupt is generated.
external devices stops bus access in the chip. Because of this, in DMA transfer to or from
external devices, the DTEND signal become disabled ("H") before the end of external bus
access. In this case the DTEND signal is not synchronized with the external bus access.
DMA End Signal Output