R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 492

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.4.3
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers. In channel 0, TGRF can also be used as a buffer register.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Note: TGRE_0 cannot be designated as an input capture register and can only operate as a
Table 12.43 shows the register combinations used in buffer operation.
Table 12.43 Register Combinations in Buffer Operation
• When TGR is an output compare register
Rev. 2.00 Sep. 07, 2007 Page 464 of 1164
REJ09B0321-0200
Channel
0
3
4
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 12.14.
compare match register.
Buffer Operation
register
Buffer
Figure 12.14 Compare Match Buffer Operation
Timer General Register
TGRA_0
TGRB_0
TGRE_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Compare match signal
Timer general
register
Comparator
Buffer Register
TGRC_0
TGRD_0
TGRF_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
TCNT