R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 383

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

11.7
11.7.1
The 37 sources of DMA requests include the software trigger and various DMA request signal
inputs.
The DMA request source for each channel is specified by the DMA request source select bits
(DTCG) in the corresponding DMA control register A (DMCNTAn).
11.7.2
For each channel of the DMAC, a synchronous circuit is incorporated to manage DMA requests,
which are asynchronously input. As a result, a blank period of a few clock cycles appears between
activation of the DMA request and actual reflection of the request in the DMA request bits
(DREQ) of DMA control register B (DMCNTBn). Figure 11.6 shows an example of timing
between the input of a DMA request and the DMA request bit.
Figure 11.6 Example of Timing between DMA Request Input and DMA Request Bit
Edge sense setting (falling edge sense)
Level sense setting (low level sense)
[Legend]
System clock
DMA request input
DMA request bit
: Sampling point for DMA request
System clock
DMA request input
DMA request bit
DMA Requests
Sources of DMA Requests
Synchronous Circuits for DMA Request Signals
DMA request bit is on input
of the valid edge
DMA request bit is set when
the active level has been sampled
at the end of two clock periods.
Section 11 Direct Memory Access Controller (DMAC)
DMA request bit is maintained regardless
of changes in the level of the DMA request input
Rev. 2.00 Sep. 07, 2007 Page 355 of 1164
DMA request bit is cleared
one cycle after sampling of
the inactive level.
REJ09B0321-0200