R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 752

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
16.6.6
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the
SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in
figure 16.17.
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Where: M: Receive margin (%)
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 2.00 Sep. 07, 2007 Page 724 of 1164
REJ09B0321-0200
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 -
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
When D = 0.5 and F = 0:
M = (0.5 - 1/(2 × 16)) × 100%
= 46.875%
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
2N
1
8 clocks
Start bit
) - (L - 0.5) F -
16 clocks
–7.5 clocks
D - 0.5
N
(1 + F) × 100 %
+7.5 clocks
D0
6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5
D1