R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 110

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 4 Clock Pulse Generator (CPG)
Notes:
Caution: 1. The frequency of the internal clock is the frequency of the signal input to the CKIO
Rev. 2.00 Sep. 07, 2007 Page 82 of 1164
REJ09B0321-0200
Clock
Operating
Mode
3
FRQCR
Setting
H'1404
H'1406
H'1414
H'1416
H'1424
H'1426
H'1444
H'1446
H'1515
H'1535
H'1555
1. The ratio of clock frequencies, where the input clock frequency is assumed to be 1.
2. In modes 0 and 2, the frequency of the clock input from the EXTAL pin or the
3. Use an internal clock (Iφ) frequency of 120 MHz or lower for the regular specifications
2. The frequency of the peripheral clock is the frequency of the signal input to the CKIO
3. The frequency multiplier of PLL circuit 1 can be selected as ×1, ×2, ×3, ×4, ×6, or ×8.
4. The signal output by PLL circuit 1 is the signal on the CKIO pin multiplied by the
frequency of the crystal resonator. In mode 3, the frequency of the clock input from
the CKIO pin.
and 100 MHz or lower for the wide-range specifications. Use a CKIO pin or bus clock
(Bφ) frequency of 60 MHz or lower. Pφ must be from 5 through 40 MHz.
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Do not set a frequency for the internal clock below the frequency of
the signal on the CKIO pin.
pin after multiplication by the frequency-multiplier of PLL circuit 1 and division by the
divider's divisor. Set the frequency of the peripheral clock to 40 MHz or below. In
addition, do not set a higher frequency for the internal clock than the frequency on
the CKIO pin.
The divisor of the divider can be selected as ×1, ×1/2, ×1/3, ×1/4, ×1/6, ×1/8, or
×1/12. The settings are made in the frequency-control register (FRQCR).
frequency multiplier of PLL circuit 1. Ensure that the frequency of the signal from PLL
circuit 1 is not more than 200 MHz.
PLL
Circuit 1
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×6)
ON (×8)
ON (×8)
ON (×8)
PLL Frequency
Multiplier
PLL
Circuit 2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Ratio of
Internal Clock
Frequencies
(I:B:P)
6:1:1
6:1:1/2
3:1:1
3:1:1/2
2:1:1
2:1:1/2
1:1:1
1:1:1/2
4:1:1
2:1:1
1:1:1
*
1
Input Clock
20
20
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 25
20 to 25
20 to 25
*
2
Output Clock
(CKIO Pin)











Selectable Frequency Range (MHz)
*
3
Internal Clock
(Iφ)
120
120
60 to 100
60 to 100
40 to 66.67
40 to 66.67
20 to 33.33
20 to 33.33
80 to 100
40 to 50
20 to 25
*
3
Bus Clock
(Bφ)
20
20
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 33.33
20 to 25
20 to 25
20 to 25
*
3
Peripheral
Clock (Pφ)
20
10
20 to 33.33
10 to 16.67
20 to 33.33
10 to 16.67
20 to 33.33
10 to 16.67
20 to 25
20 to 25
20 to 25
*
3