R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 767

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
5
4
3
Bit Name
RDRF
NACKF
STOP
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Receive Data Register Full
[Clearing conditions]
•
•
[Setting condition]
•
No Acknowledge Detection Flag
[Clearing condition]
•
[Setting condition]
•
Stop Condition Detection Flag
[Clearing condition]
•
[Setting conditions]
•
•
When 0 is written in RDRF after reading RDRF = 1
When ICDRR is read
When a receive data is transferred from ICDRS to
ICDRR
When 0 is written in NACKF after reading NACKF
= 1
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
When 0 is written in STOP after reading STOP = 1
In master mode, when a stop condition is detected
after frame transfer
In slave mode, when the slave address in the first
byte, after detecting start condition, matches the
address set in SAR, and then the stop condition is
detected
Rev. 2.00 Sep. 07, 2007 Page 739 of 1164
Section 17 I
2
C Bus Interface 3 (IIC3)
REJ09B0321-0200