R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 215

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
31 to 12
11
10, 9
8
7 to 4
3
2
1
0
Bit Name

ICF

ICE

OCF

WT
OCE
Initial
Value
All 0
0
All 0
0
All 0
0
0
0
0
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Instruction Cache Flush
Writing 1 flushes all instruction cache entries (clears the
V and LRU bits of all instruction cache entries to 0).
Always reads 0. Write-back to external memory is not
performed when the instruction cache is flushed.
Reserved
These bits are always read as 0. The write value should
always be 0.
Instruction Cache Enable
Indicates whether the instruction cache function is
enabled or disabled.
0: Instruction cache disabled
1: Instruction cache enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
Operand Cache Flush
Writing 1 flushes all operand cache entries (clears the
V, U, and LRU bits of all operand cache entries to 0).
Always reads 0. Write-back to external memory is not
performed when the operand cache is flushed.
Reserved
This bit is always read as 0. The write value should
always be 0.
Write Through
Selects write-back mode or write-through mode.
0: Write-back mode
1: Write-through mode
Operand Cache Enable
Indicates whether the operand cache function is
enabled or disabled.
0: Operand cache disabled
1: Operand cache enabled
Rev. 2.00 Sep. 07, 2007 Page 187 of 1164
REJ09B0321-0200
Section 8 Cache