R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 141

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.10
5.10.1
The value of the stack pointer must always be a multiple of four. If it is not, an address error will
occur when the stack is accessed during exception handling.
5.10.2
The value of the vector base register must always be a multiple of four. If it is not, an address error
will occur when the stack is accessed during exception handling.
5.10.3
When the stack pointer is not a multiple of four, an address error will occur during stacking of the
exception handling (interrupts, etc.) and address error exception handling will start up as soon as
the first exception handling is ended. Address errors will then also occur in the stacking for this
address error exception handling. To ensure that address error exception handling does not go into
an endless loop, no address errors are accepted at that point. This allows program control to be
shifted to the address error exception service routine and enables error processing.
When an address error occurs during exception handling stacking, the stacking bus cycle (write) is
executed. During the stacking of the status register (SR) and program counter (PC), the SP is
decremented by 4 for both, so the value of SP will not be a multiple of four after the stacking
either. The address value output during stacking is the SP value, so the address where the error
occurred is itself output. This means the write data stacked will be undefined.
Usage Notes
Value of Stack Pointer (SP)
Value of Vector Base Register (VBR)
Address Errors Caused by Stacking of Address Error Exception Handling
Rev. 2.00 Sep. 07, 2007 Page 113 of 1164
Section 5 Exception Handling
REJ09B0321-0200