R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 159

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.3.12
DMA transfer request enable register 2 (DREQER2) is an 8-bit readable/writable register that
enables/disables the SCIF (channels 4 to 7) DMA transfer requests, and enables/disables CPU
interrupt requests.
DMA transfer request enable register 2 is initialized by a power-on reset or in deep standby mode.
Bit
7
6
5
4
3
2
1
0
Bit Name
SCIF 7ch TX
SCIF 7ch RX
SCIF 6ch TX
SCIF 6ch RX
SCIF 5ch TX
SCIF 5ch RX
SCIF 4ch TX
SCIF 4ch RX
DMA Transfer Request Enable Register 2 (DREQER2)
Initial value:
Initial
Value
0
0
0
0
0
0
0
0
R/W:
Bit:
7ch TX
SCIF
R/W
0
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7ch RX
SCIF
R/W
0
6
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
6ch TX
SCIF
R/W
0
5
request enabled
disabled
6ch RX
SCIF
R/W
0
4
5ch TX
SCIF
R/W
0
3
5ch RX
Rev. 2.00 Sep. 07, 2007 Page 131 of 1164
SCIF
R/W
0
2
4ch TX
SCIF
Section 6 Interrupt Controller (INTC)
R/W
1
0
4ch RX
SCIF
R/W
0
0
REJ09B0321-0200