R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 729

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

16.3.12 Line Status Register (SCLSR)
The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can
be cleared to 0 only if it has first been read (after being set to 1).
SCLSR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit
15 to 1
0
Initial value:
Note: *
R/W:
Bit:
Only 0 can be written to clear the flag after 1 is read.
Bit Name
—
ORER
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0
12
—
R
0
11
—
R
0
R/W
R
R/(W)* Overrun Error
10
—
R
0
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*
[Clearing conditions]
•
•
1: An overrun error has occurred*
[Setting condition]
•
Notes: 1. Clearing the RE bit to 0 in SCSCR does
—
R
9
0
ORER is cleared to 0 when the chip is a power-on
reset
ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
—
R
8
0
2. The receive FIFO data register (SCFRDR)
—
R
7
0
not affect the ORER bit, which retains its
previous value.
retains the data before an overrun error
has occurred, and the next received data
is discarded. When the ORER bit is set to
1, the SCIF cannot continue the next
serial reception.
Rev. 2.00 Sep. 07, 2007 Page 701 of 1164
—
R
6
0
—
R
5
0
R
—
4
0
R
—
0
3
2
REJ09B0321-0200
R
2
—
0
R
1
—
0
R/(W)*
ORER
0
0
1