R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1181

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
Figure 16.11 Sample Flowchart
for Transmitting Serial Data
Figure 16.16 Sample Flowchart
for Transmitting/Receiving Serial
Data
Figure 17.22 Bit Synchronous
Circuit Timing
Table 17.5 Time for Monitoring
SCL
17.7.1 Issuance of Stop Condition
and Start Condition
(Retransmission)
17.7.2 Settings for Multi-Master
Operation
17.7.3 Reading ICDRR in Master
Receive Mode
18.3.1 Control Register (SSICR)
Page Revision (See Manual for Details)
716
720
764
765
766
766
774
Modified
Modified
Figure modified
Table modified
Title added
Added
Added
TEND flags in SCFSR, then clear
CKS3
1
Bit
11
Write transmit data to SCFTDR
and read 1 from TDFE and
All data transmitted?
and read 1 from TDFE and TEND
Write transmit data to SCFTDR,
these flags to 0
flags in SCFTDR, then clear
Bit Name
SPDP
CKS2
0
1
these flags to 0
Yes
Yes
Rev. 2.00 Sep. 07, 2007 Page 1153 of 1164
Main Revisions and Additions in this Edition
Description
Serial Padding Polarity
0: Padding bits are low.
1: Padding bits are high.
Note: When MUEN = 1, padding bits are
[1]
No
Time for Monitoring SCL*
33 tpcyc*
81 tpcyc*
low. (The MUTE function is given
priority.)
[1]
[1]
SCIF status check and transmit data write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and read 1
from the TDFE and TEND flags, then
clear these flags to 0.
[1] SCIF status check and transmit data
2
2
Read SCFSR and check that the
write:
TDFE flag is set to 1, then write
transmit data to SCFTDR, and
read 1 from the TDFE and TEND
flags, then clear these flags to 0.
The transition of the TDFE flag from
REJ09B0321-0200
1