R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 348

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
Table 11.3 shows the DMA source/destination address registers. For details on the rotation address
"indexing" mode, see section 11.11, Rotate Function. Note that when performing pipelined
transfer to or from external devices and modules that support burst access, make sure to set the
direction bits to select address incrementation ("001") or rotation ("011").
Table 11.3 Increment/Decrement for DMA Source/Destination Address Registers
11.3.8
DMCNTA handles the selections of the transfer mode and the condition of transfer, control of
reload functions, and selection of DMA sources.
Rev. 2.00 Sep. 07, 2007 Page 320 of 1164
REJ09B0321-0200
Transfer data size
selection bits
SZSEL
"000" (8 bits)
"001" (16 bits)
"010" (32 bits)
Bit
31, 30
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DMA Control Register A (DMCNTA)
Bit Name

31
—
15
—
R
R
0
0
30
—
14
—
R
R
0
0
"000"
(fixed)
±0
±0
±0
MDSEL[1:0]
R/W
29
13
—
R
0
0
Initial
Value
All 0
R/W
28
12
—
R
0
0
27
11
—
—
R
R
0
0
R/W
R
BRLOD SRLOD DRLOD
R/W
"001"
(plus direction)
+1
+2
+4
26
10
—
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
R/W
DSEL[1:0]
25
0
9
0
Address Indexing Mode
R/W
R/W
SAMOD or DAMOD
24
0
8
0
23
—
—
R
R
0
7
0
"010"
(minus direction)
−1
−2
−4
22
—
—
R
R
0
6
0
R/W
21
—
R
0
5
0
R/W
20
—
R
0
4
0
DCTG[5:0]
R/W
19
—
R
0
3
0
"011"
(rotation)
+1
+2
+4
R/W
18
—
R
0
2
0
R/W
R/W
STRG[1:0]
17
0
1
0
R/W
R/W
16
0
0
0