R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 466

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be
Table 12.30 Output Level Select Function
Note: The reverse phase waveform initial output value changes to active level after elapse of the
Rev. 2.00 Sep. 07, 2007 Page 438 of 1164
REJ09B0321-0200
Bit
3
2
1
0
Bit 1
OLSN
0
1
dead time after count start.
2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of
3. Clearing the TOCS bit to 0 makes this bit setting valid.
Bit Name
TOCL
TOCS
OLSN
OLSP
Initial Output
High level
Low level
written to the bit.
control.
Initial
Value
0
0
0
0
Active Level
Low level
High level
R/W
R/(W)*
R/W
R/W
R/W
1
Description
TOC Register Write Protection*
This bit selects the enable/disable of write access to the
TOCS, OLSN, and OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is
1: Write access to the TOCS, OLSN, and OLSP bits is
TOC Select
This bit selects either the TOCR1 or TOCR2 setting to
be used for the output level in complementary PWM
mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
Output Level Select N*
This bit selects the reverse phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.30.
Output Level Select P*
This bit selects the positive phase output level in reset-
synchronized PWM mode/complementary PWM mode.
See table 12.31.
Up Count
High level
Low level
enabled
disabled
Function
Compare Match Output
3
3
Down Count
Low level
High level
2