R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 576

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7
12.7.1
MTU2 operation can be disabled or enabled using the standby control register. The initial setting
is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode.
For details, refer to section 25, Power-Down Modes.
12.7.2
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 12.108 shows the input clock
conditions in phase counting mode.
Rev. 2.00 Sep. 07, 2007 Page 548 of 1164
REJ09B0321-0200
Figure 12.107 Timing for Status Flag Clearing by DMAC Activation (Channels 0 to 4)
Pφ, Bφ
Address
Status flag
Interrupt
request signal
Flag clear
signal
Usage Notes
Module Standby Mode Setting
Input Clock Restrictions
DMAC read cycle
Source addess
DMAC write cycyle
Destination addres