R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 764

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 17 I
17.3.4
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received.
ICIER is initialized to H'00 by a power-on reset or deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 736 of 1164
REJ09B0321-0200
Bit
7
6
5
I
2
Bit Name
TIE
TEIE
RIE
2
C Bus Interrupt Enable Register (ICIER)
C Bus Interface 3 (IIC3)
Initial value:
Initial
Value
0
0
0
R/W:
Bit:
R/W
TIE
7
0
R/W
R/W
R/W
R/W
TEIE
R/W
6
0
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1 or 0, this bit
enables or disables the transmit data empty interrupt
(TXI).
0: Transmit data empty interrupt request (TXI) is
1: Transmit data empty interrupt request (TXI) is
Transmit End Interrupt Enable
Enables or disables the transmit end interrupt (TEI) at
the rising of the ninth clock while the TDRE bit in ICSR
is 1. TEI can be canceled by clearing the TEND bit or
the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Receive Interrupt Enable
Enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request
(ERI) in the clocked synchronous format when receive
data is transferred from ICDRS to ICDRR and the
RDRF bit in ICSR is set to 1. RXI can be canceled by
clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) are disabled.
1: Receive data full interrupt request (RXI) are enabled.
R/W
RIE
disabled.
enabled.
5
0
NAKIE
R/W
4
0
STIE
R/W
3
0
ACKE ACKBR ACKBT
R/W
2
0
R
1
0
R/W
0
0