R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 302

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
• Single Write Timing Setting Examples
Table 9.15 SDITR Set Value Correspondence Table (Single Write Timing)
Rev. 2.00 Sep. 07, 2007 Page 274 of 1164
REJ09B0321-0200
Figure
Figure 9.39
Figure 9.40
Figure 9.41
Figures 9.39 to 9.41 show the correspondence between the timing of single write operations
and the set values of the SDRAMm timing register (SDmTR). Table 9.15 shows the
SDRAMm timing register (SDmTR) set values for each figure.
CKIO
SDRAM command
Data bus
Note: If the interval set in DRAS is longer than the period from when the WR
DRAS
010
000
000
command is issued until the DWR interval elapses, the DRAS setting
is used.
Figure 9.39 Single Write Timing Example 1
(ACT-WR)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all command
DRCD
ACT
DRCD
00
01
01
(ACT-PRA)
DRAS
(WR-PRA)
WR
DWR
d
Single write
DSL
DPCG
001
001
001
PRA
(PRA-next)
DPCG
DSL
DWR
0
0
1