R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 259

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.14
SDmTR specifies the timing for read and write accesses to SDRAM.
Bit
31 to 19 
18 to 16 DRAS[2:0] Undefined R/W
15, 14
13, 12
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAMm Timing Register (SDmTR) (m = 0, 1)
Bit Name

DRCD[1:0] Undefined R/W
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
R/W
DRCD[1:0]
29
13
—
—
Initial
Value
All 0
All 0
R
0
R/W
28
—
12
—
R
0
R/W
27
—
11
—
R
0
R/W
R
R
DPCG[2:0]
R/W
26
—
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Row Active Interval Setting
These bits specify the minimum interval that must
elapse between the SDRAM row activation command
(ACT) and deactivation (PRA).
000: 1 cycle
111: 8 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
Row Column Latency Setting
These bits specify the SDRAM row column latency.
00: 1 cycles
01: 2 cycles
10: 3 cycles
11: 4 cycles
R/W
25
—
—
R
0
9
:
DWR
R/W
24
—
—
R
0
8
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 231 of 1164
22
—
—
R
R
0
6
0
Section 9 Bus State Controller (BSC)
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
REJ09B0321-0200
R/W
R/W
18
—
—
2
DRAS[2:0]
DCL[2:0]
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0