R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 740

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-
Figure 16.8 shows an example of the operation for reception.
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REJ09B0321-0200
synchronization and starts reception.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
B. The SCIF checks whether receive data can be transferred from the receive shift register
C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error
D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: When a parity error or a framing error occurs, reception is not suspended.
data-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to
1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the
RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a
break reception interrupt (BRI) request is generated.
Serial data
RDF
FER
Figure 16.8 Example of SCIF Receive Operation (8-Bit Data, Parity, 1 Stop Bit)
the first is checked.
(SCRSR) to SCFRDR.
has not occurred.
set.
1
Start
bit
0
D 0
D 1
One frame
Data Parity
D 7
bit
RXI interrupt
request
0/1
Stop
bit
1
Start
bit
0
Data read and RDF flag
read as 1 then cleared to 0
by RXI interrupt handler
D 0
D 1
Data
D 7
Parity
bit
0/1
Stop
ERI interrupt request
generated by receive
error
bit
1
(mark state)
Idle state
1