R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 480

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.42 Setting of Bits BTE1 and BTE0
Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer
Rev. 2.00 Sep. 07, 2007 Page 452 of 1164
REJ09B0321-0200
Bit 1
BTE1
0
0
1
1
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the
to section 12.4.8, Complementary PWM Mode.
timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer
transfer will not be performed.
Bit 0
BTE0
0
1
0
1
Description
Enables transfer from the buffer registers to the temporary registers*
and does not link the transfer with interrupt skipping operation.
Disables transfer from the buffer registers to the temporary registers.
Links transfer from the buffer registers to the temporary registers with
interrupt skipping operation.*
Setting prohibited
2
1