R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 246

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
Notes: 1. Make sure the page read and page write cycle wait select (CSPRWAIT and
Rev. 2.00 Sep. 07, 2007 Page 218 of 1164
REJ09B0321-0200
Bit
10 to 8
7 to 3
2 to 0
2. Writing to the CSn wait control register 1 (CS1WCNTn) must be done while CSC for the
Bit Name
CSPRWAIT
[2:0]

CSPWWAIT
[2:0]
CSPWWAIT) settings are within the range defined by the read and write cycle wait
select (CSRWAIT and CSWWAIT) settings. Select each wait cycle number according
the system configuration incorporated.
corresponding channel is disabled (EXENB = 0). Only channel 0 (CS0) can be enabled
by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to 1
between the reset release and data write access to CS0.
Initial
Value
111
All 0
111
R/W
R
R/W
R/W
Description
Page Read Cycle Wait Select
These bits specify the number of wait states inserted
into the second and subsequent page read cycles. This
setting is valid when the page read access enable bit
(PRENB) is set to 1.
000: 0 wait state
111: 7 wait states
Reserved
These bits are always read as 0. The write value
should always be 0.
Page Write Cycle Wait Select
These bits specify the number of wait states inserted
into the second and subsequent page write cycles.
This setting is valid when the page write access enable
bit (PWENB) is set to 1.
000: 0 wait state
111: 7 wait states
:
: