R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 317

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

10.1.2
SYCBESTS1 indicates the status of slave bus (peripheral bus (1)) regarding whether a timeout
occurred, whether an illegal address access was made, or which bus master accessed the slave bus.
Table 10.2 shows the correspondence between the bus space and the slave bus.
Bit
31 to 15 
14
13
12 to 10 
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bus Monitor Status Register 1 (SYCBESTS1)
Bit Name
PER
PTO
31
15
—
—
R
R
0
0
PTO
30
14
—
R
R
0
0
PER
29
13
—
R
R
0
0
Initial
Value
All 0
0
0
All 0
28
—
12
—
R
R
0
0
27
—
11
—
R
R
0
0
R/W
R
R
R
R
26
—
10
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Timeout
This bit indicates that a timeout occurred on peripheral
bus (1) when the first bus error occurred.
0: Timeout not generated
1: Timeout generated
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (1) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
Reserved
These bits are always read as 0. The write value
should always be 0.
PMST[1:0]
25
—
R
R
0
9
0
24
—
R
R
0
8
0
23
—
—
R
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 289 of 1164
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
Section 10 Bus Monitor
19
—
—
R
R
0
3
0
REJ09B0321-0200
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0