R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 828

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 Serial Sound Interface (SSI)
(2)
Rev. 2.00 Sep. 07, 2007 Page 800 of 1164
REJ09B0321-0200
Reception Using Interrupt Data Flow Control
Yes
Figure 18.23 Reception Using Interrupt Data Flow Control
Read data from receive data register.
define SSICR configuration bits.
Wait for interrupt from SSI.
disable error interrupts,
disable data interrupts,
enable error interrupts.
enable data interrupts,
Wait for idle interrupt
Disable SSI module,
enable idle interrupt.
Enable SSI module,
Release from reset,
Receive more data?
SSI error interrupt?
from SSI module.
Start
End
No
No
Yes
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
Use SSI status register bits
after underflow/overflow.
to realign data