R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 279

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(4)
Transition to and from self-refresh mode is controlled by means of settings to SDRAM refresh
control register 0 (SDRFCNT0). Transition to and from self-refresh mode takes place
simultaneously for all channels.
An auto-refresh cycle operation takes place immediately before transition to self-refresh mode.
While in self-refresh mode the CKE signal is low level. Immediately after recovery from self-
refresh mode an auto-refresh cycle is triggered.
Figure 9.7 shows the timing of transition to self-refresh mode, and figure 9.8 shows the timing of
recovery from self-refresh mode.
Self-Refresh
CKIO
SDRAM command
Figure 9.8 Example of Timing of Recovery from Self-Refresh Mode
Figure 9.7 Example of Timing of Transition to Self-Refresh Mode
CKIO
SDRAM command
DSL: Deselect command
RFA: Auto-refresh command
RFX: Self-refresh exit command
Self-refresh mode
(CKE = L)
(DREFW Bit Set Value: 0010)
(DREFW Bit Set Value: 0010)
DSL: Deselect command
RFA: Auto-refresh command
RFS: Self-refresh entry command
Auto-refresh cycle
RFA
DREFW
DSL
Self-refresh clearing
REX
interval
DREFW
DSL
DSL
Self-refresh mode (CKE = L)
RFS
Rev. 2.00 Sep. 07, 2007 Page 251 of 1164
DSL
Section 9 Bus State Controller (BSC)
RFA
Auto-refresh
cycle
DREFW
DSL
DSL
REJ09B0321-0200