R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 436

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.4
TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5,
TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5.
Rev. 2.00 Sep. 07, 2007 Page 408 of 1164
REJ09B0321-0200
Bit
7 to 3
2
1
Bit Name
—
CMPCLR5U 0
CMPCLR5V 0
Timer Compare Match Clear Register (TCNTCMPCLR)
Initial value:
Initial
Value
All 0
R/W:
Bit:
—
R/W
R
R/W
R/W
R
7
0
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
TCNT Compare Clear 5U
Enables or disables requests to clear TCNTU_5 at
TGRU_5 compare match or input capture.
0: Disables TCNTU_5 to be cleared to H'0000 at
1: Enables TCNTU_5 to be cleared to H'0000 at
TCNT Compare Clear 5V
Enables or disables requests to clear TCNTV_5 at
TGRV_5 compare match or input capture.
0: Disables TCNTV_5 to be cleared to H'0000 at
1: Enables TCNTV_5 to be cleared to H'0000 at
—
R
5
0
TCNTU_5 and TGRU_5 compare match or input
capture
TCNTU_5 and TGRU_5 compare match or input
capture
TCNTV_5 and TGRV_5 compare match or input
capture
TCNTV_5 and TGRV_5 compare match or input
capture
—
R
4
0
—
R
3
0
CLR5U
R/W
CMP
2
0
CLR5V
R/W
CMP
1
0
CLR5W
R/W
CMP
0
0