R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 440
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 440 of 1196
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIER2_0
Rev. 2.00 Sep. 07, 2007 Page 412 of 1164
REJ09B0321-0200
Bit
7
6 to 2
1
0
Bit Name
TTGE2
—
TGIEF
TGIEE
Initial value:
Initial
Value
0
All 0
0
0
R/W:
Bit:
TTGE2
R/W
R/W
R/W
R
R/W
R/W
7
0
—
R
6
0
Description
A/D Converter Start Request Enable 2
Enables or disables generation of A/D converter start
requests by compare match between TCNT_0 and
TGRE_0.
0: A/D converter start request generation by compare
1: A/D converter start request generation by compare
Reserved
These bits are always read as 0. The write value should
always be 0.
TGR Interrupt Enable F
Enables or disables interrupt requests by compare
match between TCNT_0 and TGRF_0.
0: Interrupt requests (TGIF) by TGFE bit disabled
1: Interrupt requests (TGIF) by TGFE bit enabled
TGR Interrupt Enable E
Enables or disables interrupt requests by compare
match between TCNT_0 and TGRE_0.
0: Interrupt requests (TGIE) by TGEE bit disabled
1: Interrupt requests (TGIE) by TGEE bit enabled
—
R
5
0
match between TCNT_0 and TGRE_0 disabled
match between TCNT_0 and TGRE_0 enabled
—
R
4
0
—
R
3
0
—
R
2
0
TGIEF TGIEE
R/W
1
0
R/W
0
0
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