R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 369

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
Bit
31 to 24 DASTS
23 to 0
1, …, 24: channel 7)
Bit Name

Initial
Value
All 0
All 0
R/W
R
R
Description
When read: DMA Arbitration Status
When written: DMA Arbitration Status Clear
These bits are used to verify the status of DMA
transfer on each channel.
•
•
•
Note:
When read:
0: Operand transfer not in progress
1: Operand transfer in progress
When written:
0: Invalid
1: Clears DMA arbitration status
Reserved
These bits are always read as 0. The write value
should always be 0.
Condition for setting to "1"
The bit for a channel in which operand transfer
(non-stop transfer) has started is set to "1".
Condition for clearing to "0"
These bits are cleared to "0" by either of the
following events.
 Correct completion of single operand transfer
 A "1" is written to the bit.
(non-stop transfer).
These bits are not cleared to "0" when DMAC
operation is forcibly ended by the external DMA
transfer forcible end signal. Write "1" to these
bits to clear them.
Section 11 Direct Memory Access Controller (DMAC)
In DMA transfer to external devices, the DMA
arbitration status bit (DASTS) can be cleared
before the end of external bus access (once
the last data-write operation has started).
Rev. 2.00 Sep. 07, 2007 Page 341 of 1164
REJ09B0321-0200