R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 634
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
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Section 13 8-Bit Timers (TMR)
• TCSR_0
Rev. 2.00 Sep. 07, 2007 Page 606 of 1164
REJ09B0321-0200
Bit
7
6
5
4
3, 2
Bit Name
CMFB
CMFA
OVF
ADTE
OS[3:2]
Initial
Value
0
0
0
0
00
R/W
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
1
1
1
Description
Compare Match Flag B
[Setting condition]
•
[Clearing condition]
•
Compare Match Flag A
[Setting condition]
•
[Clearing condition]
•
Timer Overflow Flag
[Setting condition]
•
[Clearing condition]
•
A/D Trigger Enable
Selects enabling or disabling of A/D converter start
requests by compare match A.
0: A/D converter start requests by compare match A are
1: A/D converter start requests by compare match A are
Output Select 3 and 2*
These bits select a method of TMO pin output when
compare match B of TCORB and TCNT occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B occurs
disabled
enabled
When TCNT matches TCORB
When writing 0 after reading CMFB = 1
When TCNT matches TCORA
When writing 0 after reading CMFA = 1
When TCNT overflows from H'FF to H'00
When writing 0 after reading OVF = 1
(toggle output)
2
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