R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 520

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)
An example of the complementary PWM mode setting procedure is shown in figure 12.38.
Rev. 2.00 Sep. 07, 2007 Page 492 of 1164
REJ09B0321-0200
Example of Complementary PWM Mode Setting Procedure
Figure 12.38 Example of Complementary PWM Mode Setting Procedure
Inter-channel synchronization setting
Enable/disable dead time generation
Complementary PWM mode setting
Brushless DC motor control setting
<Complementary PWM mode>
Dead time, carrier cycle setting
Complementary PWM mode
PWM cycle output enabling,
Counter clock, counter clear
PWM output level setting
Enable waveform output
Start count operation
Stop count operation
source selection
TCNT setting
TGR setting
PFC setting
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[1] Clear bits CST3 and CST4 in the timer start register
[2] Set the same counter clock and clock edge for channels
[3] When performing brushless DC motor control, set bit BDC
[4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000.
[5] Set only when restarting by a synchronous clear from
[6] Set the output PWM duty in the duty registers (TGRB_3,
[7] This setting is necessary only when no dead time should be
[8] Set the dead time in the dead time register (TDDR), 1/2 the
[9] Select enabling/disabling of toggle output synchronized with
[10] Select complementary PWM mode in timer mode register 3
[11] Set enabling/disabling of PWM waveform output pin output in
[12] Set the port control register and the port I/O register.
[13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start
(TSTR) to 0, and halt timer counter (TCNT) operation.
Perform complementary PWM mode setting when
TCNT_3 and TCNT_4 are stopped.
3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and
CKEG0 in the timer control register (TCR). Use bits
CCLR2 to CCLR0 to set synchronous clearing only when
restarting by a synchronous clear from another channel
during complementary PWM mode operation.
in the timer gate control register (TGCR) and set the
feedback signal input source and output chopping or gate
signal direct output.
another channel during complementary PWM mode
operation. In this case, synchronize the channel generating
the synchronous clear with channels 3 and 4 using the timer
synchro register (TSYR).
TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4,
TGRD_4). Set the same initial value in each corresponding
TGR.
generated. Make appropriate settings in the timer dead time
enable register (TDER) so that no dead time is generated.
carrier cycle in the carrier cycle data register (TCDR) and
carrier cycle buffer register (TCBR), and 1/2 the carrier cycle
plus the dead time in TGRA_3 and TGRC_3. When no dead
time generation is selected, set 1 in TDDR and 1/2 the carrier
cycle + 1 in TGRA_3 and TGRC_3.
the PWM cycle using bit PSYE in the timer output control
register 1 (TOCR1), and set the PWM output level with bits OLSP
and OLSN. When specifying the PWM output level by using
TOLBR as a buffer for TOCR_2, see figure 12.3.
(TMDR_3). Do not set in TMDR_4.
the timer output master enable register (TOER).
the count operation.