R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 853

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.4.2
The General Status Register (GSR) is a 16-bit read-only register that indicates the status of
RCAN-ET.
• GSR (Address = H'002)
Bits 15 to 6: Reserved. The written value should always be '0' and the returned value is '0'.
Bit 5 — Error Passive Status Bit (GSR5): Indicates whether the CAN Interface is in Error
Passive or not. This bit will be set high as soon as the RCAN-ET enters the Error Passive state and
is cleared when the module enters again the Error Active state (this means the GSR5 will stay high
during Error Passive and during Bus Off). Consequently to find out the correct state both GSR5
and GSR0 must be considered.
Bit 5: GSR5
0
1
Initial value:
R/W:
Bit:
General Status Register (GSR)
15
—
R
0
14
—
R
0
Description
RCAN-ET is not in Error Passive or in Bus Off status (Initial value)
[Reset condition] RCAN-ET is in Error Active state
RCAN-ET is in Error Passive (if GSR0 = 0) or Bus Off (if GSR0 = 1)
[Setting condition] When TEC ≥ 128 or REC ≥ 128 or if Error Passive Test
Mode is selected
13
—
R
0
12
—
R
0
11
—
R
0
10
—
R
0
—
R
9
0
—
R
8
0
Section 19 Controller Area Network (RCAN-ET)
—
R
7
0
Rev. 2.00 Sep. 07, 2007 Page 825 of 1164
—
R
6
0
GSR5 GSR4 GSR3 GSR2 GSR1 GSR0
R
5
0
R
4
0
R
3
1
REJ09B0321-0200
R
2
1
R
1
0
R
0
0