R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 402

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 374 of 1164
REJ09B0321-0200
External clock: TCLKA
Internal clock:
TSTR: Timer start register
TSYR: Timer synchronous register
TCR:
TMDR: Timer mode register
TIOR:
TIORH: Timer I/O control register H
TIORL: Timer I/O control register L
TIER:
TGCR: Timer gate control register
[Legend]
Channel 3: TIOC3A
Channel 4: TIOC4A
Channel 0: TIOC0A
Channel 1: TIOC1A
Channel 2: TIOC2A
Channel 5: TIC5U
Input/output pins
Input/output pins
Timer control register
Timer I/O control register
Timer interrupt enable register
Clock input
Input pins
TIOC3C
TIOC3D
TIOC4C
TIOC4D
TIOC3B
TIOC4B
Pφ/1024
TIOC0C
TIOC0D
TIOC0B
TIOC1B
TIOC2B
TIC5W
TCLKC
TCLKD
TCLKB
Pφ/256
TIC5V
Pφ/16
Pφ/64
Pφ/1
Pφ/4
Figure 12.1 Block Diagram of MTU2
TOER: Timer output master enable register
TOCR: Timer output control register
TSR:
TCNT: Timer counter
TCNTS: Timer subcounter
TCDR:
TCBR:
TDDR:
Timer status register
Timer cycle buffer register
Timer cycle data register
Timer dead time data register
Interrupt request signals
Interrupt request signals
Channel 3: TGIA_3
Channel 4: TGIA_4
Channel 5: TGIU_5
Channel 0: TGIA_0
Channel 1: TGIA_1
Channel 2: TGIA_2
Peripheral bus
A/D converter conversion
start signal
TGRA:
TGRB:
TGRC:
TGRD:
TGRE:
TGRF:
TGRU:
TGRV:
TGRW: Timer general register W
TGIW_5
TGIC_3
TGID_3
TGIC_4
TGID_4
TGIC_0
TGID_0
TGIB_3
TGIB_4
TGIV_5
TGIB_0
TGIE_0
TGIB_1
TCIU_1
TGIB_2
TCIU_2
TCIV_3
TCIV_4
TGIF_0
TCIV_0
TCIV_1
TCIV_2
Timer general register F
Timer general register A
Timer general register B
Timer general register E
Timer general register V
Timer general register C
Timer general register D
Timer general register U