R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 261

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.15
SDmMOD specifies the values to be written to the SDRAM mode register or extended mode
register. Writing to this register causes a mode register set command or extended mode register set
command to be issued automatically to SDRAM.
Notes: The following points should be kept in mind regarding SDRAMm mode register settings.
Bit
31 to 15 
14 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
1. Make sure to set a burst length of 1 for SDRAM. Operation cannot be guaranteed with
2. The SDRAM column latency must match the setting of the SDRAM controller column
3. Check to make sure the status bits (DSRFST, DPWDST, DDPDST, and DMRSST) in
SDRAMm Mode Register (SDmMOD) (m = 0, 1)
Bit Name
DMR[14:0] Undefined R/W
settings other than burst length 1.
latency setting bits (DCL) in SDRAMC. Operation cannot be guaranteed if the latency
settings do not agree.
the SDRAM status register (SDSTR) are all cleared to 0.
31
15
—
—
R
R
0
0
R/W
30
14
—
—
R
0
R/W
29
13
—
—
Initial
Value
All 0
R
0
R/W
28
—
12
—
R
0
R/W
27
—
11
—
R
0
R/W
R
R/W
26
—
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Mode Register Setting
Writing to these bits causes a mode register set
command or extended mode register set command to
be issued to SDRAM. The setting of the DMR bits is
output as A16 to A2 signals. The distinction between
the mode register set command and extended mode
register set command is made on the bases of the
SDRAM bank address.
Write operation: A mode register set command is
issued.
DMR bit
A16 to A2 signal
R/W
25
—
—
R
0
9
R/W
DMR[14:0]
24
—
—
R
0
8
R/W
23
—
—
R
0
7
Rev. 2.00 Sep. 07, 2007 Page 233 of 1164
R/W
22
—
—
R
0
6
A16 A15
b14
↓
Section 9 Bus State Controller (BSC)
R/W
21
—
—
R
0
5
b13
↓
R/W
20
—
—
R
0
4
R/W
19
—
—
R
0
3
...
...
REJ09B0321-0200
R/W
18
—
—
R
0
2
R/W
17
—
—
R
0
1
A2
b0
↓
R/W
16
—
—
R
0
0