R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 735

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 16.3 shows a sample flowchart for initializing the SCIF.
Set RTRG[1:0], TTRG[1:0], and MCE bits
After reading ER, DR, and BRK flags
Clear TE and RE bits in SCSCR to 0
in SCFSR, and each flag in SCLSR,
Set TE and RE bits in SCSCR to 1,
Set data transfer format in SCSMR
PFC setting for external pins used
in SCSCR (leaving TIE, RIE, TE,
and set TIE, RIE, and REIE bits
in SCFCR, and clear TFRST
Set TFRST and RFRST bits
and RE bits cleared to 0)
Figure 16.3 Sample Flowchart for SCIF Initialization
and RFRST bits to 0
write 0 to clear them
Set value in SCBRR
Start of initialization
End of initialization
Set CKE[1:0] bits
SCK, TxD, RxD
in SCFCR to 1
Section 16 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Sets PFC for external pins used.
Set as RxD input at reciving and
TxD at transmission.
However, no setting for SCK pin is
required when CKE[1:0] is 00.
Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to
be used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
When the intrnal clock output is
selected, a clock starts to be output
from the SCK pin at this point.
Rev. 2.00 Sep. 07, 2007 Page 707 of 1164
REJ09B0321-0200