R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 143

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1
• 16 levels of interrupt priority can be set
• NMI noise canceller function
• Register banks
Figure 6.1 shows a block diagram of the INTC.
By setting the 14 interrupt priority registers, the priorities of the IRQ, PINT, and on-chip
peripheral module interrupts can be set to one of 16 levels for each source.
This controller provides an NMI input level bit that indicates the NMI pin state. The interrupt
exception service routine can verify the pin state by reading this bit and use the information to
implement a noise canceling function.
This LSI has register banks that enable register saving and restoration required in the interrupt
processing to be performed at high speed.
Features
Section 6 Interrupt Controller (INTC)
Rev. 2.00 Sep. 07, 2007 Page 115 of 1164
Section 6 Interrupt Controller (INTC)
REJ09B0321-0200