R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 724

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9
SCFCR resets the quantity of data in the transmit and receive data FIFO registers, sets the trigger
data quantity, and contains an enable bit for loop-back testing. SCFCR can always be read and
written to by the CPU. It is initialized to H'0000 by a power-on reset or in deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 696 of 1164
REJ09B0321-0200
Bit
15 to 8
7, 6
Initial value:
R/W:
Bit:
FIFO Control Register (SCFCR)
Bit Name
—
RTRG[1:0]
15
—
R
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
00
12
—
R
0
11
—
R
0
R/W
R
R/W
10
—
R
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register (SCFSR).
The RDF flag is set to 1 when the quantity of receive
data stored in the receive FIFO register (SCFRDR) is
increased more than the set trigger number shown
below.
•
Note: In clock synchronous mode, to transfer the receive
—
R
9
0
Asynchronous mode •
00: 1
01: 4
10: 8
11: 14
data using DMAC, set the receive trigger number
to 1. If a number other than 1 is set, CPU must
read the receive data left in SCFRDR.
—
R
8
0
R/W
RTRG[1:0]
7
0
R/W
6
0
R/W
TTRG[1:0]
5
0
Clocked synchronous mode
00: 1
01: 2
10: 8
11: 14
R/W
4
0
—
R
3
0
TFRST RFRST LOOP
R/W
2
0
R/W
1
0
R/W
0
0