R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 301
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
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CKIO
SDRAM command
Data bus
CKIO
SDRAM command
Data bus
Note: If the interval set in DRAS ends before RD, PRA is issued in the table
size after RD.
Figure 9.37 Single Read Timing Example 2
Figure 9.38 Single Read Timing Example 3
ACT: Row and bank activation command
RD:
PRA: Precharge-all command
(ACT-PRA)
ACT: Row and bank activation command
RD:
DSL: Deselect command
PRA: Precharge-all command
(ACT-PRA)
DRAS
ACT
(ACT-RD)
DRAS
(ACT-RD)
ACT
Read command
DRCD
DRCD
Read command
DSL
DSL
Single read
Single read
RD
RD
(RD-d)
DCL
PRA
(RD-d)
Rev. 2.00 Sep. 07, 2007 Page 273 of 1164
PRA
DCL
(PRA-next)
(PRA-next)
DPCG
DPCG
Section 9 Bus State Controller (BSC)
DSL
DSL
d
d
REJ09B0321-0200
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