R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 345

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
10 to 8
7 to 4
3
Bit Name
DAMOD
[2:0]

SACT
Initial
Value
Undefined R/W
All 0
Undefined R/W
R/W
R
Description
Destination Address Direction Control
These bits are used to specify the direction of counting
for the source address.
000: Fixed
001: Incrementation
010: Decrementation
011: Rotation
100 to 111: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Active Signal Output for Source
This bit is used to control the output of the DMA-active
signal (DACT) for the source corresponding to the
requesting source setting in the DCTG bits.
When this bit is set to "0", output of the DACT signal is
disabled and the signal is fixed high unless the level
changes because of the DACT bit setting.
When this bit is set to "1", output of the DACT signal is
valid ("L") from the next cycle after the start of the
DMAC read cycle.
However, while output of the DACT signal is enabled
when the DMA request source selection bits (DCTG)
are set for software triggering, a valid DACT signal
cannot be output when the requesting source is an on-
chip peripheral circuit (DCTG), regardless of the
setting of the SACT bits.
0: Stops output of the DMA-active signal for the source
1: Selects output of the DMA-active signal for the
source during read access
Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Sep. 07, 2007 Page 317 of 1164
REJ09B0321-0200